The present invention relates generally to integrated circuits, and more particularly, to quiescent current (IDDQ) verification for scan test circuitry.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital and sometimes analog components on a single chip. ICs may have manufacturing defects such as physical failures and fabrication defects that cause the ICs to malfunction. Thus, the ICs need to be tested to detect manufacturing defects. Design for test (DFT) techniques add testability features to ICs that allow automatic test equipment (ATE) to execute various fault tests using test patterns generated by an automatic test pattern generator (ATPG) on the ICs to identify manufacturing defects. ICs undergoing testing are referred to as devices-under-test (DUT).
ICs that undergo fault testing include multiple scan flip-flops that form scan chains. Specific vectors of data are shifted in one end of each scan chain and results out the other end with the results compared with expectations to detect any faults. At each vector application, the IDDQ current consumed by the circuit may be measured and compared to predetermined limits. It is important to ensure that the IDDQ measurement circuitry and instruments are operating correctly. Vectors are a set of inputs designed to test a system. Various vectors can be used to test a system's behavior in response to various inputs. Scan testing has two components: one component for functional (logic) testing, and another component for IDDQ testing. The same chain (but different vectors) is used for each.